Synchronous integrated circuits are clocked by an external clock signal and perform operations at predetermined times relative to the rising and falling edges of the external clock signal. For example, in dynamic random access memories (“DRAMs”), the timing of external signals, such as command, address and write data signals, is determined by the external clock signal, and the memory device must latch these signals at the proper times to successfully capture the signals. To latch these applied signals, an internal clock signal is developed in response to the external clock signal, and is conventionally applied to latches contained in the memory device to clock the external signals into the latches. The internal clock signal and external clock signal must be synchronized to ensure the latches are clocked at the proper times to successfully capture the external signals.
When a read request is made, a memory controller requesting the data expects data from the memory device to be available on a data bus within a predetermined read latency, which is usually a predetermined number of system clock cycles after the read request is made, e.g. eight external clock cycles. The memory device has its own internal clock system, which receives the external clock signal and develops from the external clock signal several different internal clock signals using a delay locked loop (“DLL”). Problems with maintaining read data latency arise in high speed DRAMs from the necessity to align data with the external clock using the internal clock signals generated by the DLL.
In order to meet a specified read latency the memory device must be able to count clock signals upon receiving a READ command and activate an output latch to provide the requested data relative to the read clock signal. The read clock is provided to the read latch with a desired phase relationship to the external system clock signal. During high speed operations, the amount of read clock delay relative to the read data valid time becomes essentially indeterminable, consequently making it very difficult to control the read clock signal to ensure a correct data output and a specified read latency measured in terms of external clock cycles.
One solution to these problems is disclosed in U.S. Pat. No. 6,687,185, which discloses synchronizing the variable timing of the internal clock signals derived from an external clock signal such that the read data and the read clock signal used to latch the read data arrive at the data latch in synchronism and with a specified read latency. With reference to FIG. 1, an external memory controller 102 supplies command and address signals C/A to a memory device 100 through a command/address buffer 112, which applies received buffered signals to either a command decoder 128 for decoding incoming commands from the memory controller 102 or an address decoder 132 for decoding incoming addresses from the memory controller 102. When a READ command is received, the command decoder 128 decodes the READ command and applies decoded signals to a read logic 136 control circuit that initiates a read operation on the memory array 140. The read logic 136 control circuit operates the memory array 140 to read out data from one or more memory addresses that are specified by an address received from the memory controller 102 and decoded by the address decoder 132.
The memory controller 102 additionally supplies an external clock signal EXTCLK to an input buffer 110 of the memory device 100. The input buffer 110 generates a buffered EXTCLK signal that is applied to a delay lock loop (“DLL”) 120, which generates internal clock signals for the memory device 100, including the read clock signal RDCLK. As previously discussed, the RDCLK signal is used to drive a read latch 148 so that the requested read data from the memory array 140 is properly latched to the respective DQ pad in a timeframe that meets the specified read latency. The input buffer 110 also applies the buffered EXTCLK signal to drive the command decoder 128 and the read logic 136 control circuit to decode the command and address signals in a timely manner.
The command decoder 128 additionally generates a RDSTART signal that has a fixed timing relationship to the RDCLK signal. The RDSTART signal is generated to track any changes in the RDCLK timing, and is also used to synchronize the read data from the memory array 140. When a READ command is decoded by the command decoder 128 the RDSTART signal is applied to a slave delay circuit 124, which models the DLL 120 and causes its output signal to be slaved to the RDCLK signal from the DLL 120. Therefore, any timing variations imparted on the RDCLK signal by the DLL 120 are also applied to the RDSTART signal. The slave delay circuit 124 outputs a delayed RDSTART signal that is applied to a counter 144, which also receives a specified read latency value from a mode register 130. The specified latency value may be predetermined at the time of manufacture, or may be a value from the memory controller 102. The delayed RDSTART signal enables the counter 144 to count down from an initial value using the read clock signal to the predetermined count value that represents the specified read latency for the memory device 100. Upon completing the count, the counter 144 signals the read latch 148 to synchronize latching the read data relative to the RDCLK based on the specified read latency.
Since the amount of delay that must be imposed on the RDCLK signal relative to when the read data is made available is indeterminable during high speed operations, it is very difficult to ensure the data output is correct and the specified read latency is met even with model delay circuits such as the slave delay circuit 124. In order for the slave delay circuit 124 to impart to the RDSTART signal the same delay that the DLL 120 imparts to the EXTCLK signal, the entire DLL 120 must be precisely modeled and the delays must be accurately matched. As is known to those skilled in the art, DLL circuits are generally large and cumbersome within the memory device space. Therefore, the trade-off of having a slave delay circuit 124 that accurately replicates the delay of the DLL 120 is that chip space consumption is doubled.
If other delay variations must be accounted for, additional model circuits and other compensative circuitry may also be required, such as offset circuits or additional counters. Such other circuits have been utilized to synchronize the read clock and the read data access within specified latency requirements. For example U.S. Pat. No. 7,065,001 entitled Method and Apparatus for Initialization of Read Latency Tracking circuit in High-Speed DRAM, which is assigned to the same assignee as the present invention, discloses a method of synchronizing counters in two different clock domains by generating a start signal for tracking a running count of clock pulses of a read clock signal. The start signal is generated by an initialization circuitry that includes an offset calculation. Various timing variations to the read clock signal are compensated in a circuit that includes a DLL, I/O model circuits and four separate counter circuits. As the demand for smaller high-speed memory chips continue to increase, any additional circuitry on the memory chip leads to significant loss of valuable chip space. However, if the read data is not provided at the DQ with a precise read latency, due to mismatched timing variations, the data will be corrupted and unusable.
Therefore, there is a need for a DLL circuit that accurately maintains a specified read latency while achieving a read operation synchronized to a read clock signal, but that also reduces the consumption of chip area.